片语

the combinational logic采用组合逻辑

Combinational logic circuits[电子] 组合逻辑电路

Combinational Logic Circuit Design组合逻辑电路设计

combinational logic outputs组合逻辑输出

combinational logic element组合逻辑元件

combinatorial logic[数] 组合逻辑；组合理则

combinational logic functions组合逻辑函数

combinational logic design翻译

combinational logic output组合逻辑输出

combinational logic system组合逻辑系统

英汉例句

• gray coding and encoding two one-hot state machine 2 trigger part and the combinational logic part of the combination of two states with separate machines.

  gray编码和one-hot编码两种状态机；2。触发器部分和组合逻辑部分结合与分开两种状态机。

• but, the combinational logic circuits possible isn't a most simple combinational logic circuits.

  但是利用最简逻辑函数实现的逻辑电路却不一定是最简的逻辑电路。

• this experimental quide to the digital logic comprises two parts: combinational logic and sequential logic.

  本实验指导书分为两大部分：组合逻辑，时序逻辑。

• and combinational logic circuits by using vhdl language and in two ways, comparing the merits of the two implementations and different design processes and ideas.

  并且通过应用组合逻辑电路和vhdl语言实现两种方法，对照了两种实现方法的优劣及不同的设计流程和思想。

• the results of simulation prove that the improved algorithms are feasible for evolving the digital combinational logic circuits and improve the evolvable efficiency and convergence performance.

  仿真实验结果证明了改进演化算法对于实现函数级数字组合逻辑电路的硬件演化是可行的，并且提高了演化算法的演化效率和收敛性能。

• this article describes a high-density programmable logic devices(hdpld)and architecture of generic logic block (glb), and design of ccd driver by using a combinational logic array and register in glb.

  介绍一种高密度可编程器件（hdpld）以及万能逻辑块（glb），并利用glb的组合逻辑阵列和寄存器来设计ccd驱动器的方法。

• multiplexer is a kind of combinational logic circuit, which can be selected an in-put datum among several data and sent it to out-put port.

  数据选择器是一种能从多个输入数据中有选择地将一个输入数据送到输出端的组合逻辑电路。

• this method, based on combinational logic minimization, proposes a new idea to proceed state assignment according to constrained. relation of compressed state table.

  由于该时序逻辑综合新方法在处理过程中要涉及解大型覆盖表的问题，为此提出满足压缩状态表约束关系的状态分配的简化算法。

• through examples it proves that the optimal method of the combinational logic based on the rough set is both feasible and effective.

  实例验证表明，基于粗糙集的组合逻辑优化方法是可行和有效的。

• the properties of boolean difference are made use of to derive a new method for fault testing in combinational logic circuits. this method is simpler and different from the traditional one.

  本文利用布尔差分的性质，给出了一种不同于传统的求组合逻辑线路故障测试码的新方法，对故障测试有一定的简化作用。

• according to a requirement of design, the optimum parameters of combinational logic circuits can be obtained after running the program.

  根据设计要求，通过本程序的运行，可获得最佳的组合逻辑电路的参数。

• this paper discusses implementation of optimization of single output combinational logic functions using single board computers.

  本文讨论了单输出组合逻辑优化在单板机上的实现。

• through examples it proves that the optimal method of the combinational logic based on the rough set is both feasible and effective.

  文章提出了基于粗糙集的多输出逻辑函数优化方法，并给出了相应算法；实例验证表明，基于粗糙集的组合逻辑优化方法是可行和有效的。

• this paper briefly introduces the basic method of transforming data selector into combinational logic circuit of other functions.

  简述了用数据选择器转换为其它功能组合逻辑电路的基本方法。

• n (23,12) is an asynchronous combinational logic circuit which can be implemented with 12 majestic-logic gates and 77 exclusive-or gates.

  是一个异步的组合逻辑电路，能用12个大数逻辑门和77个异或门电路来实现。

• if the combinational logic circuit is only one output, called the single-output combinational logic circuit;

  如果组合逻辑电路只有一个输出，称为单输出组合逻辑电路；

• functions of logic synthesis are to transform and optimize the combinational logic functions and produce the pure logic level structural description.

  逻辑综合的功能是对组合逻辑函数的描述进行转换和优化，生成与逻辑功能描述等价的优化的逻辑级纯结构描述。

• a special testing sequence input is need for measuring maximum dyna- mic current of a combinational logic circuit.

  组合逻辑电路的最大动态电流测试应在电路的原始输入端施加一个特定的测试序列才能实现。

• results indicate that when fault duration is shorter than phase difference of three clocks, enhanced st-tmr can almost mask the seu in combinational logic circuit and clock line.

  故障注入的结果显示，时空三模冗余技术在故障持续时间不大于三路时钟的相位差的情况下，可以很好的屏蔽组合逻辑和时钟线的单粒子翻转（seu）事件。

• to stress the application of karaugh map on designing of coding circuits in parallel-comparator adc in terms of the design of combinational logic circuits.

  根据组合逻辑电路的设计方法，突出用卡诺图化简逻辑表达式在并联比较型a/d转换器编码电路设计中的应用。

• in this paper the writer tries to integrate the design of asynchronos counters of arbitrary carry system with the design of combinational logic circuits in concept and method.

  本文试图把时序逻辑电路和组合逻辑电路的设计，在概念上和方法上统一起来。