片语

phase e locked loop锁相环路

Linear Phase-Locked Loop线性锁相回路

offset phase-locked loop偏移锁相环

Soft Phase-locked Loop软锁相环

software phase-locked loop软件锁相环

offset phase- locked loop带偏移锁相环

pulse phase-locked loop脉沖锁相环

英汉例句

• the principle of voltage linear digital triggering of thyristor by eprom is described and it is discussed to solve the frequency disturbance on digital trigger by phase locked loop .

  描述了用eprom实现晶闸管电压线性触发原理，讨论了用锁相环解决数字触发的频率扰动问题。

• then presented the basic structure, phase model, frequency response and performance analysis for noise and spur, of phase locked loop (pll).

  然后介绍了锁相环（pll）的基本结构、相位模型、频率响应、噪声及杂散性能。

• direct synthesizing and phase locked loop are combined to implement the synthesizer. ultra-light and double shock proof and high efficiency switching power supply are used in the synthesizer.

  该合成器采用了直接合成与数字锁相相结合的方法，并采用了超轻型、双重隔振技术和高效率开关电源。

• after the signals treated by a digital phase locked loop of zero phase-difference when phase and frequency following, this problem has satisfactorily been solved.

  采用对相位和频率跟蹤无相差的数字锁相环对同步信号进行处理可满意地解决上述问题。

• an example of the phase locked loop applied in the phase adjusting trigger was given in this paper. the author provided an inexpensive single channel trigger. it had a certain practicable value.

  通过介绍锁相环路技术在移相触发器中的应用及一个实际例子，提出了一种价廉的单通道触发器的新思路，具有一定的实用价值。

• a new architecture of charge pump for lowing locking time of phase locked loop (pll) is proposed.

  设计了一种减小pll锁定时间的新型电荷泵。

• the primary factor affecting fast phase lock is analyzed by using matlab. then a fast all digital phase locked loop with a high precision automatic modulus control is proposed.

  应用matlab分析了影响锁相环快速锁定的主要因素，提出了一种具有高精度自动变模控制的快速全数字锁相环。

• anovel approach to implement symbol timing recovery is presented which uses a hybrid digital phase locked loop (hdpll).

  本文介绍了一种利用混合数字锁相环（hdpll）实现码元定时恢复的新方法。

• at the same time, an adaptive phase control system configuration based on coupled phase locked loop array was proposed.

  同时，还给出了利用耦合锁相环阵列内部信号实现阵列相位自适应控制的方案。

• phase locked loop connected with phase pid control is applied in the middle loop in order to acquire good dynamic process and strong anti disturbance performance as well as high precision.

  中环引入与相位pid控制相结合的锁相环路，保证了系统在达到高稳态精度的同时具有好的动态特性和强的抗干扰能力。

• because of the fading characteristic in troposcatter channel, the mechanism of traditional phase locked loop is difficult to achieve the effect in troposcatter communication.

  由于对流层散射信道存在严重的衰落现象，故而传统的锁相环机制在散射通信中往往难以奏效。

• we present a phase locked loop (pll) frequency synthesizer for digital tuning system (dts), which is used for dts of car radio receiver.

  针对汽车音响收音数字调谐系统的实例，介绍一种广播用双波段锁相环频率合成电路的设计方法。

• according to transfer functions of the loop filter and the single phase locked loop system, it figures out the loop filters parameters, and introduces the selection of loop bandwidth.

  根据环路滤波器传递函数以及单环锁相系统的传递函数，计算出环路滤波器的各个参数，并介绍了环路带宽的选择。

• second, an enhanced phase locked loop (epll) control strategy based on improved adaptive notch filtering (anf) is proposed, controller parameters are optimized using bf-pso algorithm.

  其次，提出了一种基于改进型anf的三相epll控制策略，并用bf-pso算法对控制器参数进行优化设计。

• figure 1 shows the general form of a charge pump integer divide phase locked loop (a very common topology used for frequency synthesis).

  图1指出了整数分电流泵锁相环的一般形式（用于频率合成技术的很常见的拓扑结构）。

• an all digital phase locked loop for clock recovery from e1 signal is presented.

  提出了一种从e1信号中提取时钟的全数字锁相环。

• high precise measuring and tracking of carrier frequency-deviation is necessary to the realization of a high performance phase locked loop in carrier recovery.

  载波恢复中高精度的频偏检测与跟蹤是高性能锁相位环路实现的必要条件。

• the basic principle of phase locked loop (pll) has been introduced, and the transmission function of the phase noises of every part of pll has been analyzed.

  介绍了锁相环的基本原理，分析了锁相环各部分电路相位噪声的传递函数。

• a software phase locked loop was designed with timing recovery applied in power electronic system integration to realize the clock synchronization between power electronic building blocks.

  将时钟恢复技术应用于电力电子系统集成，设计了一个软件锁相环，实现了模块间的时钟同步。

• the controller make up of tms320f2812 dsp chip, detecting circuits include sampling circuit, modulate circuit and phase locked loop and other periphery control and drive circuit.

  本文设计的控制器以tms320f2812dsp芯片为核心，加上检测电路（包括采样电路、调理电路、锁相环等）和其它外围控制和驱动电路构成。

• this paper illuminates theory, structure, spectrum distribution, merits and defects, especially spurs of direct digital synthesis(dds), and it then introduces phase locked loop (pll) theory.

  对dds的结构、优缺点、频谱分布，特别是杂散性能进行了详细的阐述。