片语

synchronous sequential logic circuit同步时序逻辑电路

Sequential Logic Circuit Design时序逻辑电路设计

sequential control circuit顺序控制回路

Sequential Logic Circuit Technology时序逻辑电路技术

sequential logic circuit[计]

sequential switch circuit时序开关电路

automatic sequential starting circuit自动顺序起动电路

英汉例句

• testing generation for faults not testable is an important factor that reduces the efficiency of sequential circuit testing generation.

  对不可测故障进行测试产生是影响时序电路测试产生效率的一个重要因素。

• mechanism about the clock skew of synchronism sequential circuit has been presented, based on analyzing the characteristics of programmable resources and sequential circuit in fpga.

  在分析星载fpga内时序电路特性以及fpga可编程资源特性的基础上，指出了fpga内同步时序电路出现时钟偏斜现象的机理。

• this paper presents an efficient sequential circuit automatic test generation algorithm. the algorithm is based on self- adapting algorithm and uses a seventeen - valued logic model.

  本文提出了一种高效的时序电路测试生成算法，该算法是建立在自适应算法的基础上，并使用了十七值逻辑模型。

• this paper is a discussion on some teaching methods of the simplification for karnaugh map, the analysis of sequential circuit and the teaching of integrated circuits.

  对数字电路中卡诺图化简、时序电路分析和集成电路教学等三个问题的教学方法进行一定的分析和探讨。

• model checking based formal verification is a technique of this kind, and has been successful used in practice to verify complex sequential circuit designs and communication protocols.

  基于模型检测的形式化方法就是这样一种技术，并已成功地在实践中应用于对复杂的时序线路设计和通信协议的正确性验证。

• in order to cope with the clock skew, a design principle of sequential circuit in fpga for spacecraft has been provided.

  在分析星载fpga内时序电路特性以及fpga可编程资源特性的基础上，指出了fpga内同步时序电路出现时钟偏斜现象的机理。

• a method of redundancy removal in the synchronous sequential circuit is presented in this paper.

  提出了一种去除同步时序电路中冗余逻辑的方法。

• in order to eliminate the sequence conflict of synchronous sequential circuit and shorten the designable time of integrated circuits, the algorithms of retiming is deeply researched in this paper.

  本文对重定时算法进行了深入研究，目的在于消除同步时序电路的时序沖突，从而缩短集成电路的设计时间。

• the article gives the principle, method and applied example of the eprom used as sequential circuit design.

  介绍了用eprom进行时序电路设计的原理、方法和应用实例。

• the problem is timing in iterative array model. this paper discusses this problem, and gives an improved algorithm for sequential circuit testing generation.

  本文针对迭代组合阵列模型测试中产生的这些问题进行了有益的探讨，并提出了改进的时序电路测试产生算法，使之更加完善。

• the sequential circuit with ternary. flip-flops in series is proposed. the synthesis for the above circuit is discussed with an example.

  本文提出三值触发器串接时序电路，用实例阐述综合方法。