片语

sequential logic circuit[计]

SCL Sequential Control Logic顺序控制逻辑

Sequential Logic Circuit Design时序逻辑电路设计

sequential-logic equivalence-checking连续逻辑等效检验

temporal logic时序逻辑；时间逻辑

Sequential Logic Design时序逻辑设计

Sequential control logic时序控制逻辑

sequential l logic顺序逻辑

sequential processingsequential logic element循序逻辑元素

unclocked sequential logic非时钟式序列逻辑

英汉例句

• this paper studies the design theory for pneumatic sequential logic circuits.

  本文研究流体逻辑时序线路的设计理论。

• it is demonstrated that the srl can be used for both combinatorial and sequential logic functions, and as all-optical regeneration devices.

  srl不但可用来实现组合的和顺序的逻辑功能，还可用于全光再生器件。

• this paper presents a multiple fault test simulator for sequential logic circuit. the simulator is implemented in serial-parallel to save memory.

  本文给出一个时序逻辑电路的多故障测试模拟程序。

• the method is simple and being understood easily, above all and it can be put into all the synchronous sequential logic circuits.

  提出了从状态转换图中直接求得触发器的置位和复位函数，从而确定触发器的驱动方程这样一种设计同步时序逻辑电路的新方法。

• in order to avoid clock skew familiar in high-speed sequential logic circuits, buffers are placed in clock-tree.

  为了避免高速时序电路中常见的时钟偏差，在时钟树中放置了缓沖器。

• sequential logic synthesis is an important part of rtl synthesis system design.

  时序逻辑综合是rtl综合系统设计中的一个重要部分。

• the principle of using sequential logic circuit and 8031 monolithic computer for realizing continuous pulse duration measure are introduced.

  主要介绍了用时序逻辑电路实现连续脉沖宽度测量的工作原理，并讨论了采用8031单片机的实现方案。

• building the transition relation of sequential logic circuit is one of the key technologies for applying model checking method to verify the sequential logic circuit.

  有效地建立和表示时序逻辑电路的状态转移关系是应用模型检查方法验证时序逻辑电路的关键技术之一。

• furthermore, in order to avoid clock skew familiar in high-speed sequential logic circuits, negative clock skew system is used in clock routeway and buffers are placed in clock-tree.

  此外，为了避免高速时序电路中常见的时钟偏差，时钟通道采用负时钟偏差系统，并在时钟树中放置了缓沖器。

• in the design of the sequential logic circuit, redundant state is used to assign the state, so the assignment is more consistent to the a -h rule, and simple sequential structure can be obtained.

  在时序逻辑电路的设计中，利用电路所存在的冗余态来参与状态分配，更符合「a-h规则」，从而获得较简单的电路结构，并且消除了无效状态和所谓的自校正问题。

• the methods have useful reference value to using correctly flip-flops and designing sequential logic circuits.

  这些方法对于正确使用触发器和设计时序逻辑电路有重要应用参考价值。

• how to implement of sequential logic in vhdl?

  在vhdl中如何实现顺序逻辑?。

• a new method named mds is introduced in this article since the methods of designing sequential logic circuit in fundamentals of digital electronics are not so efficient and too simple.

  通用教材《数字电子技术》中介绍的传统的时序电路设计方法——状态表及状态图法过于简单，很难满足较复杂电路的设计要求。

• the race and hazard in the sequential logic circuit is quite essential and must be considered when designing logic circuit.

  时序逻辑电路中的竞争冒险是电路设计中必须考虑到的重要方面。

• in this paper, dt flip- flop excitation table is developed, the design method of sequential logic circuits using dt flip- flop is presented, and the design example using the method is given.

  导出了dt触发器的激励表，提出了应用dt触发器的时序逻辑电路的设计方法，并给出了设计实例。

• it is seen that to realize synchronous sequential logic circuits with the flip-flops is effective and convenient.

  可以看出，用这种触发器实现同步时序逻辑电路是有效且方便的。

• the circuit includes a sequential logic drive circuit, a dc bias voltage circuit and a monolithic temperature control circuit for the focal plane array.

  其中包括时序逻 辑驱动电路、直流偏置电压电路及单芯片焦平面温度控制电路。