片语

tlb vax的文本库文件格式

TLB TableLookasideBuffer表格后备缓沖器

KUYU TLB插件

tlb designtlb设计

TLB Dark镜片颜色

Tagged TLB标记的TLB

英汉例句

• A TLB miss requires accessing a page table that is stored in the main memory, which consumes considerably more processor cycles.

  如果TLB没有命中，那么就需要访问存储在主存中的页表，而这样做需要消耗相当多的处理器周期。

• TLB is the cache holding the mapping information from the virtual address to the physical page in memory.

  TLB缓存包含从虚拟地址到内存中物理页面的映射信息。

• Chart 2 correlates the performance improvements seen in Chart 1 with the decreased CPI and the corresponding decrease in TLB miss rates.

  图2将图1看到的性能提升与减少的CPI和相应减少的tlb失误率关联起来。

• Locking TLB entries can ensure that a memory access to a given region never incurs the penalty of a page table walk.

  锁定TLB输入能确保对于给出区域的内存读取绝不会导致页表移动的掉失。

• The performance improvement is due to the reduction of Translation Lookaside Buffer (TLB) misses, which occurs because the TLB can now map to a much larger virtual memory range.

  性能之所以得到了改进，是因为提高了TranslationLookasideBuffer (TLB)的命中率，这是因为TLB可以映射到更大的虚拟内存范围。

• With 16-megabyte and 16-gigabyte pages, a further improvement in TLB hit rate led to proportional CPI gains and, therefore, higher overall throughput.

  当使用 16MB和16 GB页面时，TLB命中率进一步提高，导致CPI成比例增长，从而取得了更高的总体吞吐率。

• The fewer pages would mean that the TLB process would have a higher hit ratio and therefore improved performance.

  页数越少，意味着TLB进程将具有更高的命中率，因而性能更好。

• One option is to increase the TLB size.

  一种选择是增加TLB大小。

• This is because TLB is able to map a larger virtual memory range.

  这是因为TLB能够映射更大的虚拟内存范围。

• TLB is used to try and retrieve translation work that has already occurred, and this is the first place the operating system will look for a process's translated memory segment.

  TLB用于尝试和检索已经发生的转换工作，而这是操作系统第一次查找进程的已转换内存段的地方。

• The TLB miss rate decreased by 13% compared to the same measurement for 4-kilobyte pages, thereby improving the overall performance of the workload by 13%.

  与使用4KB的页面相比，tlb失误率减少了13%，导致工作负载的整体性能提高13%。

• An increase in TLB hit rate improves the CPI metric and, therefore, performance of that program.

  提高tlb命中率可以提高CP i度量，从而也提高程序的性能。

• This difference in performance gain is predictable because the pressure on the TLB cache increases as the size of the database and the memory assigned to the DB2 buffer pools increases.

  这两组测试得到的性能结果的不同是可以预测的，因为随着数据库和分配给db2缓沖池的内存的增加，TLB缓存上的压力也随之增加。

• TLB cache entry reuse (cache hit) equates to quicker address translation and subsequently faster access to physical memory.

  tlb缓存条目重用(缓存命中)意味着更快的地址转换，还意味着对物理内存的更快的访问。

• Whenever an instruction is fetched from memory, the instruction pointer is translated via the instruction TLB into a physical address.

  无论何时从内存中取一个指令，指令指针都会经指令tlb的翻译后指向物理地址。

• Large pages can accommodate more memory in fewer actual pages, so as more large pages are used, more memory can be referenced through the TLB than with smaller page sizes.

  大内存页可以用更少的实际页来提供更多的内存，相当于较小的页大小，使用的大内存页越多，就有越多的内存可以通过TLB引用。