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BIST BuiltInSelfTest内置自测试

Memory BIST存储器内建自测试

Qala bist拉什卡尔加

LV BIST内置自测试

BIST controllerBIST控制器

Bist Qala皮斯特堡

英汉例句

• experimental results show that test velocity is k times faster than that of general bist structure, while hardware cost is equivalent to that of general bist.

  实验结果表明，该方法的测试速度比一般bist的速度快k倍（k为并行度），而硬件花费与一般bist结构相当。

• this paper makes a comparative study for loop-based bist schemes. the structures and operating modes of both serial and parallel feedback bist schemes are presented.

  对两种基于反馈的自测试（bist）方案进行了比较研究，给出了串行反馈和并行反馈bist方案的设计结构和操作模式。

• the bist structure circuit is simple and feasible, and the corresponding algorithm is easy to achieve.

  电路结构简单可行，提供的相应算法也易于实现。

• aiming at low-power bist, a novel low-power bist scheme was presented.

  针对低功耗测试问题，本文提出一种新的低功耗混合bist方案。

• absrtact: novel bist scheme for soc was presented in this paper.

  摘 要：文中提出了一种新颍的soc芯片bist方案。

• this article gives a new bist test generator design for transient current testing, this design not only produces needed test vector pairs but also has an advantage of low hardware overheads.

  本文给出了一种新型的瞬态电流测试bist测试生成器设计方案，该设计可以产生所需要的测试向量对，同时具有硬件开销小的优点。

• author「s researching in this thesis is rightly based on above facts. bst and bist theory, solution and application based on bst are studied in this thesis also.

  重点对基于边界扫描的测试算法、设计、应用和基于其上的bist设计进行了研究。

• sram bist is also combined with arm core」s boundary scan testing during system level dft.

  系统级可测性设计主要是将存储器bist与arm核的边界扫描测试相结合。

• bist theory, solution and application in fpga are studied in this thesis.

  本论文主要讨论的是可编程逻辑器件fpga的bist理论、方法和应用。

• bist has been applied into transient current testing as an effective method to reduce testing spending.

  内建自测试（bist）是一种有效降低测试开销的技术，在瞬态电流测试中得到了应用。

• in this paper, the soc design characteristics and mixed-mode testing of the bist were discussed.

  文中对soc的设计特点及其bist中的混合模式测试进行了探讨。

• to reduce the storage volume of the test data during the built-in self-test(bist), a new bist technique based on two dimensional compression of test data is presented.

  为压缩内建自测试（bist）期间所需测试数据存储容量，提出了一种新的基于测试数据两维压缩的bist方案。

• the top metal test pad, special test mode and bist are adopted in the ic circuits to solve the ic test problem about the chip function test and electric character test.

  通过添加测试引脚、设计专用测试模式，内建自测试等方法有效的解决了该芯片电路的功能测试和电气性能测试。

• the bist controller can not only perform traditional memory test algorithms but also generates test patterns required for the logic part.

  bist控制器不仅可以执行传统的存储器测试算法，而且可以生成用于逻辑模块的测试向量。

• in this thesis, we research on scan-based bist techniques of digital systems.

  本论文对数字系统基于扫描的bist技术进行了深入研究。

• the impacts of these problems were analyzed, and the corresponding solutions were presented, at the same time, a test technology combining with bist was introduced.

  分析了这些问题的影响，提出了相应措施，并介绍了结合bist技术进行逻辑簇测试的方法。

• the realizing principle and scheme of bist are discussed in this paper. an example of bist in digital display system of radar is demonstrated.

  本文论述了系统自检的技术原理和实现方案，结合雷达显示系统给出了一个具体的例子。

• a bist test pattern generator for iddt testing design. it can random generate a set of test pairs with 1~2 switches.

  设计一种用于iddt测试的bist测试向量生成器，它随机产生跳变数为1-2的测试向量对。

• for the linear analog circuits, a bist method based on the system′s state variables is presented.

  本文针对线性模拟电路，提出了一种基于系统状态变量的bist方法。