片语

clock-data skew时钟

clock skew detail时钟偏移

clock skew schedule时钟偏斜调度

Zero-Skew Clock Tree零偏差时钟树

relative clock skew相对时钟频差

clock skew restraint抑制数字系统中的时钟偏斜

Bounded-Skew Clock Tree有界偏差时钟树

clock skew scheduling时钟偏差规划

useful clock skew有效时钟偏斜

英汉例句

• our basic idea is to make use of the permissible clock skew to enhance the timing reliability of a circuit.

  我们的基本想法，是利用可允许的时序差异值来提高电路的时序可靠度。

• fix: the kerberos authentication protocol requires that the clock skew between a server and a client is no greater than 5 minutes.

  解决方案：kerberos身份验证协议要求服务器和客户机之间的时钟差不大于5分钟。

• clock signal and clock skew become more and more important in the circuit performance.

  时钟信号和时钟偏差对电路性能的影响也越来越明显。

• in clock routing, clock signal and clock skew become more and more important for impact of the circuit performance.

  在时钟布线中，时钟信号和时钟偏差对电路性能的影响越来越明显。

• a yield driven clock skew scheduling algorithm is proposed in presence of process variations.

  针对工艺参数变化的情况，提出一种成品率驱动的时钟偏差安排算法。

• clock tree synthesis is important in the backend-end design of chip design, and the clock skew has become the major part of constraints that limit system clock frequency.

  时钟树综合是芯片后端设计至关重要的一环，时钟偏差成为限制系统时钟频率的主要因素。

• after analyzing the clock delay, the clock skew and the critical steady synchronizer which are difficult in the design, some settle methods are introduced.

  同时就设计中常遇到的三个问题：时钟延时，时钟偏移，同步器的亚稳态性加以说明且提出了解决方法。

• in this thesis, we show that how ffs are connected by pds can also greatly influence the final clock skew due to limitations of a practical adb and pd design.

  在这篇论文中，我们提出由于实际的可调变延迟缓 沖器及相差侦测器设计上有其物理上的限制，相差侦测器连接正反器的拓墣也 会影响最后的时脉偏移。

• furthermore, in order to avoid clock skew familiar in high-speed sequential logic circuits, negative clock skew system is used in clock routeway and buffers are placed in clock-tree.

  此外，为了避免高速时序电路中常见的时钟偏差，时钟通道采用负时钟偏差系统，并在时钟树中放置了缓沖器。

• concerning the clock skew and clock drift problem in wireless sensor networks, some different methods of synchronization time on synchronization accuracy were studied.

  针对无线传感器网络固有的时钟偏移和时钟漂移问题，研究了不同的时间同步方法对同步精度的影响。

• a new clock skew scheduling algorithm is proposed. this algorithm generates timing constraints which can effectively promote the area optimization of logic syn thesis.

  提出了一种新的时钟偏斜规划算法，该算法所生成的时序约束可以有效地促进逻辑综合工具的面积优化。

• we first analyze the worst-case clock skew of pd connection structures.

  在这篇论文中，我们首先分析给定相差侦测器架构下最糟的时脉偏移量。

• in order to avoid clock skew familiar in high-speed sequential logic circuits, buffers are placed in clock-tree.

  为了避免高速时序电路中常见的时钟偏差，在时钟树中放置了缓沖器。

• mechanism about the clock skew of synchronism sequential circuit has been presented, based on analyzing the characteristics of programmable resources and sequential circuit in fpga.

  在分析星载fpga内时序电路特性以及fpga可编程资源特性的基础上，指出了fpga内同步时序电路出现时钟偏斜现象的机理。

• this paper presents an effective approach for clock skew scheduling that can reduce the center error square and assign slacks incrementally.

  本文提出了一种有效的方法时钟歪斜调度中心可以减少误差平方和增量分配的休閑裤。

• clock skew is in a synchronization digital integrated circuit design difficult problem.

  时钟偏移是同步数字集成电路设计中的一个难题。

• experiment results show that this approach can efficiently reduce area of logic synthesis results compared with the traditional clock skew scheduling algorithm, without degrading the performance.

  实验结果表明：按权重分配裕量的方法相对于平均分配裕量，能够在不降低电路性能的情况下，更加有效地降低逻辑综合结果的面积。

• in multi-fpga designs, the delay of clock transfer causes a huge clock skew between fpgas and therefore undermines the system performance.

  在多fpga设计中，时钟信号的传输延时造成了fpga间的大时钟偏差，进而制约系统性能。