The digital realization of monostable circuit and extraction of bit-synchronous signal with digital phase lock loop are also introduced in detail.
对于其中的单稳态电路的数字化和数字锁相环提取位同步信号也进行了详细的设计说明。
The phase lock loop is a feedback control system that makes two telecommunication signals' phase synchronization, suitable to the synchronous trigger circuit of the convertor device.
锁相环路是完成两个电信号相位同步的反馈控制系统,适宜于变流装置的同步触发电路之中。
The principle of phase lock loop and its application in the motor power-measuring system are introduced, furthermore the design and analysis of the circuit for constant speed control are provided.
The electronic design is similar to the one for crystal oscillator lock loop but the parameters are different.
腔自动调谐的电路设计和晶体振蕩器伺服环路类似,仅仅环路参数不同。
Because of the frequency lock loop traction PLL filter can be designed very narrow, with very good noise suppression performance, to meet the precise requirements of carrier phase tracking.
The orthogonal analog phase lock loop is used to get the timing information of the impulse radio system and the multi-path component separation.
使用正交模拟锁相环路对无载波的脉沖无线电系统实现多径捕获和同步提取。
Digital phase lock loop is a key part of the digital demodulator.
数字锁相环是数字解调器的关键部件。
In the new scheme proposed, the phase lock loop is avoided and the digital logical circuit is used.
该方案利用信号自身的特性,采用数字逻辑设计,有效避免了性能不高的锁相环的使用。
The performance of synchronization tracking using pilot is analyzed, followed by a numerical method to determine the optimal lock loop parameters to minimize average bit error rate (BER).
分析了利用导频同步跟蹤的性能,以及提出了一个数值方法确定最优环路参数以最小化误码率。
Phase lock loop and benchmark resistance compensating technologies were used to improve the detection precision, the error was less than 10%.
通过锁相放大技术及基準电阻补偿方法提高了测量的精度,误差在10%以内。
Digital phase lock loop base on fuzzy logical control, which is used to recover carrier in communication system.