its main reason is that the power assumption of digital circuits in test mode is very higher than that in normal system operation mode.
在可测试性设计中考虑功耗的主要原因是数字电路在测试方式下的功耗比系统在正常工作方式下高很多。
better yet, a kernel splice interrupts normal system operation for a mere fraction of a millisecond, leaving daemons, processes, and connections intact.