片语

PLL IC锁相环电路

PLL Circuit锁相环频率合成

RF PLL锁相环

Enhanced PLL增强型锁相环

PLL IIC频率合成方式

PLL type及芯片编号

PLL Synthesized相位锁定频率合成

PLL Reconfiguration锁相环重配置

PLL Jitter回路时基

英汉例句

• Digital PLL and digital filter are built based on conventional double closed-loop control which contains voltage loop and current loop.

  前者在常规的采用电压外环、电流内环的双闭环控制基础上，搭建数字锁相环、数字滤波器。

• The nonlinear characteristics of PLL system are analyzed comprehensively in this thesis for the first time.

  首次对电机锁相控制系统的非线性问题进行了较全面的研究工作。

• It studies the noise mechanism and its impact on loop stability of PLL circuits and obtains some noise reductive measures, which have proved to be better.

  研究了噪声的产生机制和对锁相环稳定性的影响，提出了减小噪声对锁相环性能影响的系列措施，实践证明，达到了较好的效果。

• It has an innovation point in the paper, PLL (Phase Locking Loop) is used for tracking, it makes ECT system capacitance testing for more precise.

  创新点是使用了锁相环达到对相位进行跟蹤，使ECT系统的电容检测变得更加精确。

• A new method is presented for analyzing the acquisition behavior of second-order PLL with sinusoidal phase detector in the absence of noise.

  本文给出了一种计算无噪声时具有正弦鑒相器的二阶锁相环捕捉特性的新方法，求得了每个差频周期的平均角频率牵引量。

• To aim at the defect of the simulate trigger and the digital trigger with microcomputer, a new universal digital trigger based on CPLD and PLL is introduced.

  提出了一种以复杂可编程逻辑器件（CPLD）和锁相环技术为核心的新型通用数字触发器，对其硬件电路和软件设计进行了详细分析。

• In order to minimize the PLL jitter, it is recommended to avoid active signal on the TEST output.

  为了尽量减少抖动的锁相环，建议，以避免在测试输出的积极信号。

• A new method which employs PLL to design vehicle detectors is presented in this paper. The designing of deferent parts of the detecting system is discussed and analyzed.

  给出了一种利用锁相环构造车辆检测系统的方法，并就该系统各部分的设计进行了分析和讨论。

• In PLL frequency synthesizers, dual modulus prescaler is a bottleneck in achieving a higher operation speed.

  在锁相环频率合成器中，双模前置分频器是一个速度瓶颈。

• Due to the frequency pulling of FLL, the passband of the filter in PLL can be made very narrow to suppress the noise, and the PLL can lock carrier's phase with high accuracy.

  由于有锁频环的频率牵引，锁相环路滤波器可以设计得很窄，具有很好的抑噪性能，满足精确跟蹤载波相位的要求。

• In the field of communications, PLL synthesizers playing an increasingly important role.

  在通信领域中，锁相环频率合成器起着越来越重要的角色。

• In this paper the principle and design of a microcomputer-controlled PLL frequency synthesis digit tuning system is discussed.

  本文叙述了一个用微机控制的锁相环频率合成数字调谐系统的原理和设计。

• When coincidence between horizontal sync and oscillator frequency is detected, the search mode is replaced by a normal PLL operation.

  当水平的同步和振动者频率之间的巧合被发现的时候，搜寻模态被正常PLL操作代替。

• Compared with conventional PLL threshold extended demodulator, it features wider capture range, shorter capture time and significant improvement in threshold level.

  与常规pll门限扩展解调器相比，它具有捕获范围宽，捕获时间短，门限改善量显着等优点。

• The PLL frequency synthesizing technic, which develops fast recent years, has been the main design scheme of signal source, because of its performance advantage.

  近年来迅速发展的锁相环频率合成技术，以其自身性能优势，逐渐成为射频信号源的主要设计方案。

• In this paper, a new method of PLL lock detector will be presented.

  在本文中，我们将展现一个新的锁相环锁定检测方法。

• This system works on UHF frequency brand, use PLL circuit. There are 256 frequencies for your option.

  本机工作在UHF频率，采用PLL锁相环电路，预设256个可选择使用频率。

• Actually, the bulk of the work in determining an optimal PLL configuration is wrapped up in determining the list of all possible configurations that meet our needs.

  实际上，确定PLL最优配置的大部分工作是确定所有的满足我们需求的配置清单。