all of the latch-up paths may have an effect on each other or one another due to different triggering dose rate, holding voltage and holding current and then one or more latch-up windows may appear.
各个闭锁路径因触发剂量率和闭锁维持电压、闭锁维持电流不同而相互影响,可能产生一个或多个闭锁窗口。
it is also indicated, based on analysis, that the latch-up may be avoided if cmos circuits work in safe section, and it can be realized by taking all kinds of measures, such as adjusting the layout …
通过分析表明,只要让cmos电路工作在安全区,闩锁效应是可以避免的,这可以通过版图设计规则和工艺技术,或者两者相结合的各种措施来实现。
the switching action of the comparator and diode d3 prevents latch-up due to a large positive-boost transient.
比较器和二极管d3的切换行动防止由于一个瞬间的正极充电引起的闭锁。
transient gamma irradiation experiment on 「qiangguang i」 indicates that a latch-up window appears in the test circuit as predicated.
「强光i」瞬时伽马辐照实验显示,实验电路像预计的那样出现了闭锁窗口。
several problems about latch-up experience in the reliability design of multiplex power supply systems are studied. a solution to the problems is proposed based on the cause analysis of latch-up.
对在多级电源系统可靠性设计中遇到的几个关于闩锁的问题进行了研究,针对闩锁产生的原因进行分析,并提出解决方法。
based on the analysis of two protection methods, an over-current protection circuit which can improve the integrated regulators latch-up effect is proposed.
对在多级电源系统可靠性设计中遇到的几个关于闩锁的问题进行了研究,针对闩锁产生的原因进行分析,并提出解决方法。
based on this, a 「three-path」 latch-up model is developed to explain the window phenomena.
在此基础上,提出了解释窗口现象的「三径」闭锁模型。
some data sheets contain electrostatic discharge or latch-up test results and the associated jedec test conditions.
有的数据手册还包括静电或闩锁测试结果以及对应的jedec测试条件。
the technology method for ic to overcome single-event upset and single-event latch-up is suggested.
提出提高集成电路抗单粒子翻转和单粒子闭锁的技术路径。
after we analyze the latch-up characteristic of cmos integrated circuits in detail, a three-path latch-up model is developed and used to explain the latch-up window phenomena reasonably.
许多研究工作用于解释闭锁窗口现象,获得了不同程度的成功。本文在分析闭?。
in power ic, crosstalk between high voltage power devices and low voltage devices can cause circuit operation failure and even latch-up .
在功率集成电路中,高压功率器件会对周围的低压电路产生串扰,从而造成电路失效甚至闭锁等现象。
problems with high on-resistance that are seen in traditional vertical structure dmosfet still appear in ldmosfet and phenomena of turn-off delay and latch-up are seen in ligbt as well.
传统垂直式dmosfet高导通电阻的缺点在ldmosfet中依旧存在,而垂直式igbt关闭延迟和闩锁的现象,也在ligbt中发生。